1. Field of the Invention
The present invention relates to a compound semiconductor memory, and, more particularly, to a fine non-volatile memory which is writable, readable and erasable.
2. Description of the Related Art
The mobility of a compound semiconductor like GaAs is greater by a factor of five to ten than Si at room temperature, so that the use of a compound semiconductor like GaAs for electronic devices can improve the operation speed. In this respect, the use of a compound semiconductor like GaAs has also been proposed in the field of non-volatile memories.
For instance, the memory structures which use two-dimensional electron gas stored at the interface between n-alGaAs layer and GaAs layer are disclosed in Examined Japanese Patent Publication No. Hei 57-162470 and Unexamined Japanese Patent Publication No. Sho 61-7666. These memory structures are hereinafter called "first prior art" and "second prior art," respectively.
FIG. 1 presents a cross-sectional view of a non-volatile memory according to the first prior art. An n-alGaAs layer 2 is formed on an n-GaAS substrate 1, with an undoped GaAs thin film 3 formed on the n-AlGaAs layer 2. A first insulating film 4 is selectively formed of an oxide film on the undoped AlGaAs thin film 3, and a floating gate 5 of a high melting point metal or polycrystalline silicon or the like is formed on the first insulating film 4. A second insulating film 6 is so formed as to cover the floating gate 5.
A gate electrode 7 is formed on the second insulating film 6, and a source electrode 8 and a drain electrode 9 are selectively formed in the regions on the undoped GaAs thin film 3 where the first insulating film 4 is not formed. A substrate electrode 10 is formed at the back of this n-GaAs substrate 1.
Data can be written in or erased from the thus constituted non-volatile memory by storing positive or negative charges in the floating gate 5. In a read mode, an electron accumulated layer is formed at the interface between the n-AlGaAs layer 2 and the undoped GaAs thin film 3, so that the reading operation speed of the non-volatile memory can be increased by using this electron accumulated layer.
According to the first prior art, however, because the floating gate 5 of polycrystalline silicon or the like is formed on the undoped GaAs thin film 3 via the first insulating film 4 of SiO.sub.2 or the like, the frequency dispersion of the capacitance-voltage (C-V) characteristic becomes greater due to, particularly, a large surface level present at the interface between the GaAs thin film 3 and the SiO.sub.2 (first insulating film 4). This impairs the operational stability and reliability.
FIG. 2 presents a cross-sectional view of a non-volatile semiconductor memory device according to the second prior art. Epitaxially grown in order on a semiconductive GaAs substrate 11 are a first undoped GaAs layer 12, a first undoped AlGaAs layer 13, a first n type AlGaAs layer 14, a second undoped AlGaAs layer 15, a second undoped GaAs layer 16, a third undoped AlGaAs layer 17, a third undoped GaAs layer 18, a fourth undoped AlGaAs layer 19 and a second n type AlGaAs layer 20.
Formed on the n type AlGaAs layer 20 is an n type GaAs layer 21 in which a recess 29 is provided. The bottom of the recess 29 is selectively opened, thus exposing the second n type AlGaAs layer 20. A gate electrode 22 is formed on the exposed surface of the second n type AlGaAs layer 20. Further, a source electrode 23 and a drain electrode 24 are formed on the n type GaAs layer 21, apart from each other with the recess 29 in between. Respectively formed under those electrodes 23 and 24 are a source region 27 and a drain region 28 which are to be electrically connected to the second undoped GaAs layer 16.
According to the thus constituted non-volatile semiconductor memory device, a first two-dimensional electron gas layer 25 and a second two-dimensional electron gas layer 26, which store electrons in a write mode, are respectively formed in the third undoped GaAs layer 18 and in the second undoped GaAs layer 16. Because the third undoped AlGaAs layer 17, which has a smaller electron affinity than those of the third undoped GaAs layer 18 and the second undoped GaAs layer 16, is formed between those layers 18 and 16, however, the first two-dimensional electron gas layer 25 and the second two-dimensional electron gas layer 26 are electrically isolated completely from each other. The second prior art thus stably keeps the data written state without reducing the electrons stored in the two-dimensional electron gas layers 25 and 26.
According to the second prior art, however, the insulation between the third undoped GaAs layer 18 equivalent to a floating electrode and the source electrode 23 and drain electrode 24 is insufficient so that the time for retaining the electrons stored in the first two-dimensional electron gas layer 25 becomes shorter.
Unexamined Japanese Patent Publication No. Hei 4-23474 discloses a compound semiconductor device which has a floating electrode between the gate electrode and the drain electrode. This device will be called "third prior art."
FIG. 3 is a cross-sectional view of a compound semiconductor device according to the third prior art. An operation layer 34 of GaAs, an undoped AlGaAs layer 35 and an i-GaAs layer 36 are formed in order on a semiconductive GaAs substrate 31, and a control gate 37 is selectively formed on the surface of the resultant structure. A floating gate 38 surrounded by an insulating film 40 is so formed on the control gate 37 and i-GaAs layer 36 as to cover those layers 37 and 36. Further, a write electrode 39 is formed on the insulating film 40.
Further, two ohmic electrodes (source and drain electrodes) 41 are formed apart from each other on that region of the i-GaAs layer 36 where the insulating film 40 is not formed. A high concentration conductive layer 33 is formed in the substrate surface under those electrodes 41.
When electrons are not stored in the floating gate 38 in the thus constituted compound semiconductor device, a slight depletion layer is formed on the surface of the operation layer 34 by the surface level between the i-GaAs layer 36 and the insulating film 40. But, this depletion layer is not large enough to block the current which passes the channel. When electrons are injected into the floating gate 38, positive charges are induced on the surface of the operation layer 34, causing the depletion layer to fill up the channel region.
As the floating gate 38 is capable of changing the widths of the depletion layer between the gate and drain electrodes and between the source and gate electrodes to adjust the surface potential of the channel, the threshold voltage can be controlled. It is therefore possible to reduce the gate voltage, thus improving the breakdown voltage of the device.
Because the insulating film 40 of SiO.sub.2 is formed on the i-GaAs layer 36, however, the third prior art like the first prior art suffers the reduction of the operational stability and reliability. The third prior art also suffers an increase in the device area, a decrease in integration density and a complicated manufacturing method.
Unexamined Japanese Patent Publication No. Hei 5-235367 discloses a non-volatile memory which is designed to prevent the reliability of the device characteristic from decreasing. This memory will be called "fourth prior art."
FIG. 4 is a cross-sectional view of a non-volatile memory according to the fourth prior art. An undoped GaAs layer 52 and an n-GaAs layer 53 are formed in order on a GaAs substrate 51. A first AlGaAs layer 54 having a large band gap is selectively formed on the n-GaAs layer 53 to be thick enough to pass the tunnel current, and an n.sup.+ -GaAs layer 55 having a small band gap is formed on the first AlGaAs layer 54. Formed on the n.sup.+ -GaAs layer 55 is a second AlGaAs layer 56 which covers this n.sup.+ -GaAs layer 55 and is thick enough not to pass the tunnel current. That is, the n.sup.+ -GaAs layer (floating electrode) 55 is surrounded by the AlGaAs layers 54 and 56 which have large band gaps.
A gate electrode 57 is formed on the second AlGaAs layer 55, and a drain electrode 58 and a source electrode 59 are selectively formed on the region of the n-GaAs layer 53 where the first AlGaAs layer 54 is not formed.
According to the thus constituted compound semiconductor memory, since the floating electrode is formed by a semiconductor layer (n.sup.+ -GaAs layer 55) of a high density impurity, it is possible to prevent the reliability of the device characteristic from decreasing by the surface level.
Because the peripheral portion of the floating electrode is all formed by semiconductor layers (AlGaAs layers 54 and 56) having the same band gaps, electrons to be stored in the floating electrode cannot be trapped sufficiently. In other words, the third and fourth prior arts have a difficulty to satisfy both the reduction of the voltages need to write and erase data and the improvement of the effect of trapping the stored electrons in the floating electrode.
As apparent from the above, no conventional memory structures have been developed yet which can satisfy the reduction of the device area, the reduction of the required voltages and the improvement of the operational stability and reliability.